logic block
英 [ˈlɒdʒɪk blɒk]
美 [ˈlɑːdʒɪk blɑːk]
网络 逻辑块; 逻辑模块; 逻辑方块; 逻辑区段; 逻辑区块
双语例句
- You can then add your required logic and block any connection that does not fit the allowed pattern.
然后，可以添加需要的逻辑，并阻塞不符合上述模式的连接。 - First in our list of subroutines is a simple logic block to check if the accelerometer is available for reading
在我们的子程序清单中首先是一个简单的逻辑块，用来检查是否有加速器可读 - The logic block is only reached if the focused application is the same between input reads.
仅当输入读取之间的获得焦点的应用程序是同一个应用程序时，才会到达逻辑块。 - I think perhaps in the past female intuition and logic have been the one stumbling block, the weak link in his armor, and for that he is always on his guard.
我猜想过去他曾被女性的直觉和逻辑所困扰过，成为他心防的薄弱一环，所以他才总是摆出一副不近人情的态度。 - To incorporate the latest developments in the configurable RAM block, it has a certain amount of research on the configurable FIFO control logic that embedded in the RAM block.
本文还结合了目前可配置存储器模块的最新发展，对嵌入在可配置存储器模块中的可配置FIFO控制器进行了研究。 - This paper presented the design and implementation of two sequential circuits in FPGA configurable logic block, namely, distributed RAM and shift register.
本文主要研究高性能FPGA可编程逻辑单元中分布式RAM和移位寄存器两种时序功能的设计实现方法。 - This method begins with selecting logic element ( LE) with minimum connectivity factor as the seed of the packing, and then uses a heuristic function based on routability-driven to obtain the most appropriate LE to pack into the configurable logic block ( CLB).
选择连接因子最小的节点作为种子节点；采用基于布通率的启发式函数来选择最合适的逻辑单元（LE）装箱到可配置逻辑单元（CLB）内部。 - Some Classes of Majority Logic Decodable Codes Based on Block Designs
几类基于组合设计的新的择多逻辑可译码 - The programmable digital devices implement the logical function by designed internal logic array block while the traditional digital systems do it by designed printed circuit block.
传统的数字系统通过设计线路板实现系统性能，而可编程器件是通过设计芯片内部的互联逻辑来实现系统功能。 - The present paper describes the structure and the function of logic control of ICU, and shows the circuit block diagram of ICU.
描述了该控制单元的结构、逻辑控制功能，以及实现该控制单元的硬件电路和软件。 - The RISC MCU core is based on Harvard architecture with 14-bit instruction length and 8-bit data length and two-level instruction pipeline The performance of the RISC MCU has been improved by replacing micro-program with direct logic block.
设计的RISCMCU采用14位字长指令总线和8位字长数据总线分离的Harvard结构和二级指令流水设计，并使用硬布线逻辑代替微程序控制，加快了微控制器的速度，提高了指令执行效率。 - This paper presents multiple-valued logic variable comparison principle including the circuit construction block diagram, working principle, truth table, and characteristic equation of 10-valued D flip flop based on above discussion.
本文首先介绍了由多值逻辑变量比较定理提出的十值D触发器的电路结构框图，分析了它的工作原理，作出了它的特性表、特性方程； - Based on above, the control logic block based on MAX ⅱ is designed.
在此基础上，设计了基于MAXⅡEPM1270芯片的逻辑控制系统。 - The Research on Distribution of FPGA Logic Block Pins
FPGA逻辑块管脚分布的研究 - The functions, logic block diagram, judgement, troubleshooting and application of WSB-12 type protection system for generator based on PC are described in the paper.
介绍了WSB－12型微机式发电机低励磁失步保护装置的功能、逻辑框图、判据、异常工况的处理及在系统中的应用。 - Primary policy of design is sorting and distilling logic function block& LFB first, then choose the language of configuration and LFB development for MSR.
设计的主要方针是首先分类和提取出逻辑功能模块LFB，接着选择MSR使用的配置及LFB开发语言。 - The improved breaker failure protection logic together with specific setting computation principle of current block will further improve the reliability of breaker failure protection for generator-transformer unit.
改进后的失灵保护逻辑加上明确的电流判别整定计算原则，将使发变组失灵保护更加完善可靠。 - This article describes a high-density programmable logic devices ( HDPLD) and architecture of generic logic block ( GLB), and design of CCD driver by using a combinational logic array and register in GLB.
介绍一种高密度可编程器件（HDPLD）以及万能逻辑块（GLB），并利用GLB的组合逻辑阵列和寄存器来设计CCD驱动器的方法。 - The paper discusses DCS's control is affected both by the control block period and phase and by the difference of time between contact input and external input flag in a programmable logic block. briefly introduces the improvements about DCS's control configuration in debugging.
本文探讨了DCS控制功能块执行周期，相位，梯形逻辑块中接点输入和逻辑输入被接收的时间差异等，对控制性能的影响，简介了有关控制组态在调试中的改进方法。 - The Error Correction for Multivalued Logic Using Linear Block codes
多值逻辑的线性分组码纠错 - Universal Packing Algorithm for FPGA Based on Logic Block Modeling
基于对可编程逻辑块建模的FPGA通用装箱算法 - At present, it is not dialectical logic scholars who block the development of logic science.
当今之世，摧残了逻辑科学发展的并不是辩证逻辑学者。 - Utilizing the concept of logic block server, it provides the reliable data block storage and implements redundant storage capacity.
利用逻辑块服务器实现逻辑块的冗余存取，实现数据块的安全存放； - Chapter III focuses on two methods for monitoring and controlling RTGs remotely via network, i.e. PLC controlled semi-object simulation and whole software simulation. Further discussion about logic control block diagram and the control flow charts of RTGs 'main organs are presented later.
第三章论述了网络化场地吊的两种仿真构架，分别是PLC控制设备半实物化仿真和纯软件化仿真，并进一步讨论了逻辑控制框图及场地吊设备主要运行机构仿真控制流程图。 - The paper analyses the feasibility and the foreground of the appliance of designing PCI bus interface with programmable logic, then puts forward the PCI target interface block diagram according to the designing demand and a circuit design scheme.
文中分析可编程器件在PCI总线产品设计中的可行性和应用前景以及PCI总线从模块接口电路的结构，提出子电路模块的具体实现方案。 - A fine-grained mapping approach is proposed according to the analysis of the detailed configurable logic block structure of FPGA device, and it is applied to the design of a systolic array for modular multiplication based on FPGA.
通过分析FPGA可配置逻辑块的细致结构，提出了一种基于FPGA的细粒度映射方法，并使用该方法高效实现了大数模乘脉动阵列。 - The method can be used to establish FPGA architecture model. Ten parts of information are contained in it, such as logic block information, wire segment information and so on.
FPGA结构描述方法包含逻辑单元信息，互连线信息等10部分。 - Nios ⅱ custom instructions is an user logic block which is connected with the ALU from the CPU data path.
NiosⅡ的自定制指令是与CPU的数据通路中的ALU相连的用户逻辑块。 - Effective transposition logic is designed by using registers and Block RAM resources within FPGA.
利用FPGA的寄存器和BlockRAM资源，设计出高效的按位转置运算逻辑。 - The effects of two positioning of the pins on the logic block ( full perimeter and top/ bottom pin positioning) on routing area are analyzed by CAD experiments, and the number of physical locations for each logic block pins is determined.
通过CAD实验研究了四周型和上下型两种逻辑块管脚分布对布线面积的影响，确定了每个逻辑管脚应当出现的物理管脚数。